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integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 pin configuration recommended application: pcie gen 2 & qpi compliant ck410b (ck410b+) clock for intel-based servers output features: 4 - 0.7v current-mode differential cpu pairs 5 - 0.7v current-mode differential src pair 4 - pci (33mhz) 3 - pciclk_f, (33mhz) free-running 1 - 48mhz 2 - ref, 14.318mhz features/benefits: supports spread spectrum modulation, 0 to -0.5% down spread on cpu outputs uses external 14.318mhz crystal and external load capacitors for low ppm synthesis error cpu clocks independent of src/pci clocks d2/d3 smbus address pcie gen 2 and qpi clock for intel-based servers functionality key specifications: low drift pcie clocks for non-transparent bridging (ntb) pcie gen 2 compliant src outputs qpi & fbd compliant cpu clocks cpu cycle-cycle jitter: < 50ps src cycle-cycle jitter: < 125ps pci cycle-cycle jitter: < 500ps cpu output skew: < 50ps src output skew: < 250ps 100ppm frequency accuracy on all outputs 56-pin tssop fs_c 1 fs_b 1 fs_a 2 cpu mhz src mhz pci mhz ref mhz u sb mhz 0 0 0 266.67 0 0 1 133.33 0 1 0 200.00 0 1 1 166.67 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 11 1n/a 1. fs_b and fs_c are three-level inputs. please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs_a is a low-threshold input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. 100.00 33.33 14.32 48.00 vddpci 1 56 fs_c/test_sel gndpci 2 55 ref0 pciclk0 3 54 ref1 pciclk1 4 53 vddref pciclk2 5 52 x1 pciclk3 6 51 x2 gndpci 7 50 gndref vddpci 8 49 fs_b/test_mode pciclk_f0 9 48 fs_a pciclk_f1 10 47 vddcpu pciclk_f2 11 46 cpuclkt0 vdd48 12 45 cpuclkc0 48mhz 13 44 vddcpu gnd48 14 43 cpuclkt1 vddsrc 15 42 cpuclkc1 srcclkt0 16 41 gndcpu srcclkc0 17 40 cpuclkt2 srcclkc1 18 39 cpuclkc2 srcclkt1 19 38 vddcpu gndsrc 20 37 cpuclkt3 srcclkt2 21 36 cpuclkc3 srcclkc2 22 35 vdda srcclkc3 23 34 gnda srcclkt3 24 33 iref vddsrc 25 32 nc srcclkt4 26 31 vtt_pwrgd#/pd srcclkc4 27 30 sdata vddsrc 28 29 sclk 932s431 advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. idt reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners.
2 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 pin description pin # pin name pin type description 1 vddpci pwr power supply for pci clocks, nominal 3.3v 2 gndpci pwr ground pin for the pci outputs 3 pciclk0 out pci clock output. 4 pciclk1 out pci clock output. 5 pciclk2 out pci clock output. 6 pciclk3 out pci clock output. 7 gndpci pwr ground pin for the pci outputs 8 vddpci pwr power supply for pci clocks, nominal 3.3v 9 pciclk_f0 out free running pci clock not affected by pci_stop# . 10 pciclk_f1 out free running pci clock not affected by pci_stop# . 11 pciclk_f2 out free running pci clock not affected by pci_stop# . 12 vdd48 pwr power pin for the 48mhz output.3.3v 13 48mhz out 48mhz clock output. 14 gnd48 pwr ground pin for the 48mhz outputs 15 vddsrc pwr supply for src clocks, 3.3v nominal 16 srcclkt0 out true clock of differential src clock pair. 17 srcclkc0 out complement clock of differential src clock pair. 18 srcclkc1 out complement clock of differential push-pull src clock pair. 19 srcclkt1 out true clock of differential src clock pair. 20 gndsrc pwr ground pin for the src outputs 21 srcclkt2 out true clock of differential src clock pair. 22 srcclkc2 out complement clock of differential src clock pair. 23 srcclkc3 out complement clock of differential src clock pair. 24 srcclkt3 out true clock of differential src clock pair. 25 vddsrc pwr supply for src clocks, 3.3v nominal 26 srcclkt4 out true clock of differential src clock pair. 27 srcclkc4 out complement clock of differential src clock pair. 28 vddsrc pwr supply for src clocks, 3.3v nominal
3 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 pin description (continued) pin # pin name t yp e pin descri p tion 29 sclk in clock pin of smbus circuitry, 5v tolerant. 30 sdata i/o data pin for smbus circuitry, 3.3v tolerant. 31 vtt_pwrgd#/pd in vtt_pwrgd# is an active low input used to determine when latched inputs are ready to be sampled. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks, plls and the crystal oscillator are stopped. 32 nc n/a no connection. 33 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 34 gnda pwr ground pin for the pll core. 35 vdda pwr 3.3v power for the pll core. 36 cpuclkc3 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 37 cpuclkt3 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 38 vddcpu pwr supply for cpu clocks, 3.3v nominal 39 cpuclkc2 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 40 cpuclkt2 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 41 gndcpu pwr ground pin for the cpu outputs 42 cpuclkc1 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 43 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 44 vddcpu pwr supply for cpu clocks, 3.3v nominal 45 cpuclkc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 46 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 47 vddcpu pwr supply for cpu clocks, 3.3v nominal 48 fs_a in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 49 fs_b/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 50 gndref pwr ground pin for the ref outputs. 51 x2 out crystal output, nominally 14.318mhz 52 x1 in crystal input, nominally 14.318mhz. 53 vddref pwr ref, xtal power supply, nominal 3.3v 54 ref1 out 14.318 mhz reference clock. 55 ref0 out 14.318 mhz reference clock. 56 fs_c/test_sel in 3.3v tolerant input for cpu frequency selection. low voltage threshold inputs, see input electrical characteristics for vil_fs and vih_fs values. test_sel: 3-level latched input to enable test mode. refer to test clarification table
4 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 ICS932S431A is a main clock synthesizer for ck410b-generation intel server platforms. ICS932S431A is driven with a 14.318mhz crystal. it generates cpu outputs up to 400mhz and pci-express clocks at 100. the 48 mhz usb clock is an exact 48.000 mhz clock. the ICS932S431A generates all other clocks with less the +/- 300 ppm error. general description block diagram power groups cpu pll control logic xtal osc. cpuclk(3:0) fixed pll 48mhz divider dividers ref(1:0) srcclk(4:0) s data sclk x1 x2 iref fs(c:a) vtt_pwrgd#/pd src/pci pll dividers test_sel pciclk(3:0), pciclk_f(2:0) vdd gnd 53 50 xtal, ref 1,8 2,7 pciclk outputs 15,25,28 20 srcclk outputs 35 34 master clock, cpu analog 12 14 48mhz, pll_48 47,44,38 41 cpuclk clocks description pin number
5 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 absolute maximum rating parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd_a - v dd + 0.5v v 1 3.3v logic input supply voltage vdd_in - gnd - 0.5 v dd + 0.5v v 1 storage temperature ts - -65 150 c 1 ambient operatin g tem p tambient - 0 7 0 c 1 case temperature tcase - 115 c 1 input esd protection hbm esd prot - 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. electrical characteristics - input/supply/common output parameters paramete r symbo l conditions* min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 low threshold input- hi g h volta g e v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v 1 low threshold input- low volta g e v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating supply current i dd3.3op full active, c l = full load; 350 ma 1 all diff pairs driven 70 ma 1 all differential pairs tri-stated 12 ma 1 input frequency f i v dd = 3.3 v 14.31818 mhz 2 pin inductance l p in 7nh1 c in logic inputs 5 pf 1 c ou t output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization t stab from vdd power-up or de- assertion of pd to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd cpu output enable after pd de-assertion 300 us 1 tfall_pd pd fall time of 5 ns 1 trise_pd pd rise time of 5 ns 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4ma1 sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. 2 input frequency should be measured at the ref pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. input low current powerdown current i dd3.3pd input capacitance
6 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 electrical characteristics - src 0.7v current mode differential pair paramete r symbo l conditions* min typ max units notes current source output impedance zo vo = vx 3000 ? 1 voltage high vhigh 660 850 mv 1,3 volta g e lo w vlo w -150 150 mv 1, 3 max volta g evovs 1150mv1 min volta g e vuds -300 mv 1 crossin g volta g e (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vx variation of crossing over all edges 140 mv 1 rise time tr vol = 0.175v, voh = 0.525v 175 525 ps 1 fall time tf voh = 0.525v vol = 0.175v 175 525 ps 1 rise time variation d-tr vol = 0.175v, voh = 0.525v 125 ps 1 fall time variation d-tf voh = 0.525v vol = 0.175v 125 ps 1 long term jitter t jlt measurement from differential wavefrom @ 10 us 0300500ps1 duty cycle dt3 measurement from differential wavefrom 45 55 % 1 skew tsk3 vt = 50% 250 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 125 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , i ref = 475 ? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . statistical measurement on sin g le ended si g nal measurement on single ended si g nal usin g absolute value. electrical characteristics - cpu 0.7v current mode differential pair parameter symbol conditions* min typ max units notes current source output impedance zo vo = vx 3000 ? 1 voltage high vhigh 660 850 mv 1,3 voltage low vlow -150 150 mv 1,3 max voltage vovs 1150 mv 1 min voltage vuds -300 mv 1 crossing voltage (abs) vx(abs) 250 550 mv 1 crossing voltage (var) d-vx variation of crossing over all edges 140 mv 1 rise time tr v ol = 0.175v, v oh = 0.525v 175 525 ps 1 fall time tf v ol = 0.175v, v oh = 0.525v 175 525 ps 1 rise time variation d-tr v ol = 0.175v, v oh = 0.525v 125 ps 1 fall time variation d-tf v ol = 0.175v, v oh = 0.525v 125 ps 1 duty cycle dt3 measurement from differential wavefrom 45 55 % 1 skew tsk3 across all cpu outputs, vt = 50% 50 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 50 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , i ref = 475 ? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i re f = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . statistical measurement on single ended signal measurement on single ended signal using absolute value.
7 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 electrical characteristics - pciclk/pciclk_f parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 33.33mhz output nominal 29.9970 30 30.0030 ns 2 absolute clock period t pabs 33.33mhz output including jitter 29.4970 30.5030 ns 2 clock high time t hi gh 1.5v 12 n/a ns 1 clock low time t low 1.5v 12 n/a ns 1 output impedance r dsp v o = v d d *(0.5) 12 55 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 edge rate t slewr/f rising/falling edge rate 1 4 v/ns 1 rise time t r v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 group skew t skew v t = 1.5 v 250 ps 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, (unless otherwise specified) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818mhz output high current i oh output low current i ol electrical characteristics - usb48mhz parameter symbol conditions* min typ max units notes lon g accurac y pp m see t p eriod min-max values 0 0 pp m1,2 clock period t p eriod 48.00mhz output nominal 20.8333 20.83333 20.8333 ns 2 absolute clock period t pabs 48.00mhz output including jitter 20.4833 21.1833 ns 2 output impedance r dsp v o = v dd *(0.5) 12 55 ? 1 output high voltage v oh i oh = -1 ma 2.4 v 1 clock high time t high 1.5v 8.094 10.036 ns 1 clock low time t lo w 1.5v 7.694 9.836 ns 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 edge rate t slewr/f_usb rising/falling edge rate 1 2 v/ns 1 rise time t r_usb v ol = 0.4 v, v oh = 2.4 v 1 2 ns 1 fall time t f_usb v oh = 2.4 v, v ol = 0.4 v 1 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 group skew t skew v t = 1.5 v 250 ps 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 350 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818mhz output high current i oh output low current i ol
8 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 electrical characteristics - ref parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 0 100 ppm 1,2 clock period t p eriod 14.318mhz output nominal 69.8343 69.84128 69.8483 ns 2 absolute clock period t pabs 14.318mhz output including jitter 68.8343 70.8483 ns 2 clock high time t hi g h 1.5v 27.533718 n/a ns 1 clock low time t low 1.5v 27.533718 n/a ns 1 output high voltage v o h i oh = -1 ma 2.4 v 1 output low voltage v o l i o l = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v o h @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 edge rate t slewr/f rising/falling edge rate 1 4 v/ns 1 rise time t r1 v o l = 0.4 v, v o h = 2.4 v 0.5 2 ns 1 fall time t f1 v o h = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 skew t sk1 v t = 1.5 v 500 ps 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t j c y c-c y c v t = 1.5 v 1000 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818mhz output high current i oh output low current i ol electrical characteristics - differential jitter parameters parameter symbol conditions min typ max units notes t jphasepll pcie gen 1 30 86 ps (p-p) 1,2 t jphaselo pcie gen 2 10khz < f < 1.5mhz 0.9 3 ps (rms) 1,2 t jphasehigh pcie gen 2 1.5mhz < f < nyquist (50mhz) 1.9 3.1 ps (rms) 1,2 t jphfbd1_3.2 g fbd1 3.2/4g 11mhz to 33mhz 1.9 3 ps (rms) 1,2 t jphfbd1_4.0 g fbd1 4.8g 11mhz to 33mhz 1.4 2.5 ps (rms) 1,2 t jphqpi qpi 133mhz 6.4gb_12ui cpu outputs onl y 0.18 0.5 ps (rms) 1,2 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. jitter, phase 2 see http://www.pcisig.com for compelte specs
9 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 5 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 0 300 ppm 1 clock period t p eriod 14.318mhz output nominal 69.82033 69.86224 ns 1 absolute min/max clock period t abs nominal 68.82033 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 skew t sk1 v t = 1.5 v 500 ps 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t j c y c-c y c v t = 1.5 v 1000 ps 1 1 guaranteed by design, not 100% tested in production.
10 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 single-ended output terminations test load cl=5pf rs zo ICS932S431A sepp output buffer (single ended push pull) rs zo rs zo sepp output buffer (single ended push pull) cl=5pf cl=5pf the singled-ended outputs of the ics 932s4231a default to a drive strength of 2 loads. the ref clocks can be turned down to 1-load strength via the smbus. suggested termination resistors are as follows for transmission lines with zo = 50 ohms: driving 1 load, rs = 33 ohms driving 2 loads, rs = 7.5 ohms single-ended outputs at 1-load strength (ref clock only) driving 1 load, rs = 22 ohms single-ended outputs at 2-load strength (power up default for all single-ended outputs)
11 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 general smbus serial interface information for the ICS932S431A how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
12 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 smbus table: output enable register pin # name control function type 0 1 pwd bit 7 srcclk7 enable output enable rw disable-hi-z enable 1 bit 6 srcclk6 enable output enable rw disable-hi-z enable 1 bit 5 srcclk5 enable output enable rw disable-hi-z enable 1 bit 4 srcclk4 enable output enable rw disable-hi-z enable 1 bit 3 srcclk3 enable output enable rw disable-hi-z enable 1 bit 2 srcclk2 enable output enable rw disable-hi-z enable 1 bit 1 srcclk1 enable output enable rw disable-hi-z enable 1 bit 0 srcclk0 enable output enable rw disable-hi-z enable 1 smbus table: output enable register pin # name control function type 0 1 pwd bit 7 ref1 enable output enable rw disable-low enable 1 bit 6 ref0 enable output enable rw disable-low enable 1 bit 5 cpuclk3 output enable rw disable-hi-z enable 1 bit 4 cpuclk2 output enable rw disable-hi-z enable 1 bit 3 0 bit 2 cpuclk1 output enable rw disable-hi-z enable 1 bit 1 cpuclk0 output enable rw disable-hi-z enable 1 bit 0 spread spectrum enable (cpu outputs only) spread off/on rw spread off spread on 0 smbus table: output enable register pin # name control function type 0 1 pwd bit 7 pciclk3 output enable rw disable-low enable 1 bit 6 pciclk2 output enable rw disable-low enable 1 bit 5 pciclk1 output enable rw disable-low enable 1 bit 4 pciclk0 output enable rw disable-low enable 1 bit 3 pciclk_f2 enable output enable rw disable-low enable 1 bit 2 pciclk_f1 enable output enable rw disable-low enable 1 bit 1 pciclk_f0 enable output enable rw disable-low enable 1 bit 0 48mhz enable output enable rw disable-low enable 1 smbus table: stop control register pin # name control function type 0 1 pwd bit 7 pciclk_f2 stop en rw free-running stoppable 1 bit 6 pciclk_f1 stop en rw free-running stoppable 1 bit 5 pciclk_f0 stop en rw free-running stoppable 1 bit 4 srcclk4 stop en rw free-running stoppable 1 bit 3 srcclk3 stop en rw free-running stoppable 1 bit 2 srcclk2 stop en rw free-running stoppable 1 bit 1 srcclk1 stop en rw free-running stoppable 1 bit 0 srcclk0 stop en rw free-running stoppable 1 reserved byte 3 10 9 11 13 3 11 42,43 10 26,27 9 23,24 21,22 free-running control, default: not affected by pci/src_stop (byte 4, bit 5) 16,17 18,19 21,22 23,24 4 cpu byte 2 byte 0 na na 26,27 na byte 1 55 39,40 18,19 54 36,37 16,17 45,46 6 5
13 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 smbus table: stop and power down mode drive control register pin # name control function type 0 1 pwd bit 7 cpuclk3 pd drive drive mode in pd rw driven hi-z 0 bit 6 cpuclk2 pd drive drive mode in pd rw driven hi-z 0 bit 5 cpuclk1 pd drive drive mode in pd rw driven hi-z 0 bit 4 cpuclk0 pd drive drive mode in pd rw driven hi-z 0 bit 3 cpuclk3 stop en rw free-running stoppable 1 bit 2 cpuclk2 stop en rw free-running stoppable 1 bit 1 cpuclk1 stop en rw free-running stoppable 1 bit 0 cpuclk0 stop en rw free-running stoppable 1 smbus table: stop and power down mode drive control register byte 5 pin # name control function type 0 1 pwd bit 7 0 bit 6 src stop drive mode driven in stop rw driven hi-z 0 bit 5 src pd drive mode dr iv en in pd rw driven hi-z 0 bit 4 0 bit 3 cpuclk3 stop drive drive mode in stop rw driven hi-z 0 bit 2 cpuclk2 stop drive drive mode in stop rw driven hi-z 0 bit 1 cpuclk1 stop drive drive mode in stop rw driven hi-z 0 bit 0 cpuclk0 stop drive drive mode in stop rw driven hi-z 0 smbus table: test mode and fs readback register pin # name control function type 0 1 pwd bit 7 test mode selection test mode selection rw hi-z ref/n 0 bit 6 test clock mode entry test mode rw disable enable 0 bit 5 0 bit 4 ref drive strength 1x or 2x rw 1x 2x 1 bit 3 pci_stop control stop non-free running pc and src clocks. rw stop run 1 bit 2 fs_c fs_c readback r latch bit 1 fs_b fs_b readback r latch bit 0 fs_a fs_a readback r latch smbus table: vendor & revision id register pin # name control function type 0 1 pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 reserved reserved see 932s431 functionality table vendor id byte 7 - byte 4 src src 36,37 39,40 42,43 - free-running control, default: not affected by cpu_stop reserved - pci, src 54,55 - - - byte 6 - 39,40 36,37 39,40 45,46 42,43 42,43 45,46 - - 45,46 36,37 - revision id (0 for a rev) - - - -
14 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 smbus table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw 0 bit 6 bc6 rw 0 bit 5 bc5 rw 0 bit 4 bc4 rw 0 bit 3 bc3 rw 0 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 smbus table: device id register pin # name control function type 0 1 pwd bit 7 did7 r - - 0 bit 6 did6 r - - 0 bit 5 did5 r - - 1 bit 4 did4 r - - 1 bit 3 did3 r - - 1 bit 2 did2 r - - 0 bit 1 did1 r - - 1 bit 0 did0 r - - 1 smbus table: m/n programming & control register pin # name control function type 0 1 pwd bit 7 m/n_en cpu and src m/n programming enable rw disable enable 0 bit 6 cpu_stop control stop non-free running pc and src clocks. rw stop run 1 bit 5 0 bit 4 0 bit 3 src alternate frequency (96% of nominal) set src = 96 mhz and pci = 32 mhz only active if byte 10, bit 2 = 1 rw normal alternate frequency 0 bit 2 cpu alternate frequency (96% of nominal) only active if latched frequency is 166 mhz or 333 mhz. set alternate cpu frequency: 166 mhz to 160 mhz 333 mhz to 320 mhz rw normal alternate frequency 0 bit 1 ref1 drive strength 1x or 2x rw 1 bit 0 ref0 drive strength 1x or 2x rw 1 reserved device id (3b hex) byte count programming b(7:0) writing to this register will configure how many bytes will be read back, default is 8 bytes. (0 to 7) reserved byte 8 byte 9 byte 10 - - - - - - cpu - cpu 54 see ref drive strength functionality table 55 src, pci - - - -
15 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 smbus table: cpu frequency control register pin # name control function type 0 1 pwd bit 7 cpu n div8 n divider prog bit 8 rw x bit 6 cpu n div9 n divider prog bit 9 rw x bit 5 cpu m div5 rw x bit 4 cpu m div4 rw x bit 3 cpu m div3 rw x bit 2 cpu m div2 rw x bit 1 cpu m div1 rw x bit 0 cpu m div0 rw x smbus table: cpu frequency control register pin # name control function type 0 1 pwd bit 7 cpu n div7 rw x bit 6 cpu n div6 rw x bit 5 cpu n div5 rw x bit 4 cpu n div4 rw x bit 3 cpu n div3 rw x bit 2 cpu n div2 rw x bit 1 cpu n div1 rw x bit 0 cpu n div0 rw x smbus table: cpu spread spectrum control register byte 13 pin # name control function type 0 1 pwd bit 7 cpu ssp7 rw x bit 6 cpu ssp6 rw x bit 5 cpu ssp5 rw x bit 4 cpu ssp4 rw x bit 3 cpu ssp3 rw x bit 2 cpu ssp2 rw x bit 1 cpu ssp1 rw x bit 0 cpu ssp0 rw x smbus table: cpu spread spectrum control register pin # name control function type 0 1 pwd bit 7 0 bit 6 cpu ssp14 rw x bit 5 cpu ssp13 rw x bit 4 cpu ssp12 rw x bit 3 cpu ssp11 rw x bit 2 cpu ssp10 rw x bit 1 cpu ssp9 rw x bit 0 cpu ssp8 rw x the decimal representation of m and n divider in byte 11 and 12 will configure the cpu vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] m divider programming bit (5:0) these spread spectrum bits in byte 13 and 14 will program the spread pecentage of cpu the decimal representation of m and n divider in byte 11 and 12 will configure the cpu vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] spread spectrum programming bit(7:0) n divider programming byte12 bit(7:0) and byte11 bit(7:6) - - byte 12 byte 14 - - spread spectrum programming bit(14:8) reserved these spread spectrum bits in byte 13 and 14 will program the spread pecentage of cpu - - - - - - - - - - - - - - - - - - - - byte 11 - - - - - - - -
16 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 smbus table: src/pci frequency control register pin # name control function type 0 1 pwd bit 7 src n div8 n divider prog bit 8 rw x bit 6 src n div9 n divider prog bit 9 rw x bit 5 src m div5 rw x bit 4 src m div4 rw x bit 3 src m div3 rw x bit 2 src m div2 rw x bit 1 src m div1 rw x bit 0 src m div0 rw x smbus table: src/pci frequency control register pin # name control function type 0 1 pwd bit 7 src n div7 rw x bit 6 src n div6 rw x bit 5 src n div5 rw x bit 4 src n div4 rw x bit 3 src n div3 rw x bit 2 src n div2 rw x bit 1 src n div1 rw x bit 0 src n div0 rw x smbus table: src/pci spread spectrum control register pin # name control function type 0 1 pwd bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x smbus table: src/pci spread spectrum control register pin # name control function type 0 1 pwd bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x reserved reserved reserved reserved reserved reserved reserved reserved reserved byte 18 byte 16 - - - - - - reserved reserved the decimal representation of m and n divider in byte 15 and 16 will configure the src vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] m divider programming bits reserved reserved reserved reserved reserved - byte 17 - n divider programming b(7:0) the decimal representation of m and n divider in byte 15 and 16 will configure the src vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 14.318 x [ndiv(9:0)+8] / [mdiv(5:0)+2] - - - - - - - - byte 15
17 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 smbus table: cpu programmable output divider register pin # name control function type 0 1 pwd bit 7 cpudiv3 rw x bit 6 cpudiv2 rw x bit 5 cpudiv1 rw x bit 4 cpudiv0 rw x bit 3 x bit 2 x bit 1 x bit 0 x smbus table: src and pci programmable output divider register pin # name control function type 0 1 pwd bit 7 pcidiv3 rw x bit 6 pcidiv2 rw x bit 5 pcidiv1 rw x bit 4 pcidiv0 rw x bit 3 src_div3 rw x bit 2 src_div2 rw x bit 1 src_div1 rw x bit 0 src_div0 rw x smbustable: test byte register test type pwd bit 7 rw 0 bit 6 rw 0 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 0 note: do not write to bit 21. erratic device operation will result! byte 19 byte 20 - - - see cpu, src and pci divider ratios table see cpu, src and pci divider ratios table reserved reserved reserved reserved cpu divider ratio programming bits see cpu, src and pci divider ratios table ics only test reserved ics only test reserved ics only test reserved ics only test reserved ics only test reserved ics only test reserved ics only test reserved test function test result ` ics only test reserved byte 21 - src_ divider ratio programming bits - - - - pci divider ratio programming bits - - - -
18 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 ref drive strength functionality byte6, bit 4 byte 10, bit 1 byte 10, bit 0 ref1 ref0 0x x 1x1x 10 0 1x1x 10 1 1x2x 11 0 2x1x 11 1 2x2x cpu, src and pci divider ratios div(3:0) divider 0 0000 2 1 0001 3 2 0010 5 3 0011 15 4 0100 4 5 0101 6 6 0110 10 7 0111 30 8 1000 8 9 1001 12 10 1010 20 11 1011 60 12 1100 16 13 1101 24 14 1110 40 15 1111 120
19 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 pd is an asynchronous active high input used to shut off all clocks cleanly prior to system power down. when pd is asserted, all clocks will be driven low before turning off the vco. all clocks will start without glitches when pd i s de-asserted. pd, power down d pu p c# u p cc r s# c r si c p / f i c pb s uf e re t o n 0l a m r o nl a m r o nl a m r o nl a m r o nz h m 3 3z h m 8 4z h m 8 1 3 . 4 11 1r o 2 * f e r i t a o l f t a o l f2 * f e r i t a o l f r o t a o l fw o lw o lw o l1 notes: 1. refer to smbus byte 4 for additional information. pd should be sampled high by 2 consecutive cpu# rising edges before stopping clocks. all single ended clocks will be held low on their next high to low transition. all differential clocks will be held high on the next high to low transition of the complimentary clock. if the control registe r determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. when the drive mode corresponding to the cpu or src clock of interest is set to '0' the true clock will be driven high at 2 x iref and the complementary clock will be tristated. if the control register is programmed to '1' both clocks will be tristated. see smbus bytes 4 and 5 for additional information. pd assertion pd cpu, 133mhz cpu#, 133mhz src, 100mhz src#, 100mhz usb, 48mhz pci, 33mhz ref, 14.31818
20 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 the time from the de-assertion of pd or until power supply ramps to get stable clocks will be less than 1.8ms. if the drive mode control bit for pd tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mv in less than 300 s of pd deassertion. pd de-assertion pd tstable <1.8ms tdrive_pwrdwn# <300 s, >200mv cpu, 133mhz cpu#, 133mhz src, 100mhz src# 100mhz usb, 48mhz pci, 33mhz ref, 14.31818 test clarification table comments fs_c/test _sel hw pin fs_b/test _mode hw pin test entry bit b6b6 ref/n or hi-z b6b7 output 0 x 0 x normal 10x0hi-z 10x1ref/n 11x0ref/n 11x1ref/n 0x10hi-z 0x11ref/n b6b6: 1= enter test mode, default = 0 (normal operation) b6b7: 1= ref/n, default = 0 (hi-z) hw s w power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode fs_c./test_sel -->3-level latched input if power-up w/ v>2.0v (-0.3v) then use test_sel if power-up w/ v<2.0v (-0.3v) then use fs_c fs_b/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 during power-up, test mode can be invoked through b6b6. if test mode is invoked by b6b6, only b6b7 is used to select hi-z or ref/n fs_b/test_mode pin is not used. cycle power to disable test mode, one shot control
21 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information part / order number shipping packaging package temperature 932s431aglf tubes 56-pin tssop 0 to +70c 932s431aglft tape and reel 56-pin tssop 0 to +70c "lf" suffix to the part number are the pb-free configuration and are rohs compliant. "a" denotes the revision designator (will not correlate to datasheet revision).
22 integrated circuit systems, inc. ICS932S431A datasheet 1426a?11/12/09 revision history rev. issue date description page # 0.1 12/10/2007 1. initial release - 0.2 7/8/2008 romoved ssop ordering information. - 0.3 9/17/2008 updated electrical characteristics, ppm and clock period data various 0.4 10/22/2009 updated datasheet title (added qpi) and key specification bullets 1 a 11/12/2009 released to final.

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